1. Field
Example embodiments of the present invention relate generally to a delay locked loop circuit, and in particular, a delay locked loop circuit capable of preventing or minimizing a failure of a coarse locking during a locking operation of a delay locked loop.
2. Related Art
There is a movement towards developing dynamic random access memories (hereinafter, referred to as ‘DRAM’), generally adapted as main memories of electronic systems, with a high degree of integration and high speed.
DRAMs are volatile memories which include memory cells as units, are readable and writable, and require being refreshed. Each of the memory cells includes one access transistor and one storage capacitor.
Improved high-speed, high-performance DRAMs include SDRAMs, DDR SDRAMs, FCRAMs, etc. In case of SRAM, writing or reading data is possible only at either rising or falling edges of a clock. In case of DDR SDRAM, writing or reading data is possible at falling edges as well as rising edges. Therefore, the data transmission speed of DDR SDRAM is twice that of SDRAM.
For example, if a memory system operates at 400 MHz and transmits data at all rising and falling edges of a clock, the effective data transmission speed per pin is 800 Mb/s. At this time, the bit time for data is 1.25 ns, which is very short. In order to meet these strict timing requirements, an interface circuit requires a circuit for synchronizing the phase of an internal on-chip clock with the phase of an external system clock. If an external clock may be internally used, internal circuits may cause clock skew. A delay locked loop (hereinafter, referred to as ‘DLL’) is used to synchronize the phase of an internal clock with the phase of the external clock, thereby compensating such clock skew.
A general delay locked loop for high-performance DRAM delays and locks an external clock, thereby generating an internal clock in sync with the external clock. The internal clock may be used as a timing control signal to output data.
Frequency ranges which DLLs cover have been extended from a low frequency of 250 MHz to a high frequency of 1 GHz with an increase in operation frequencies of electronic systems or semiconductor memory devices adapted in electronic systems.
In case of a DLL circuit having an additional coarse locking function for increasing the operation speed of a DLL, a failure of a coarse locking may occur in a low-frequency inversion locking operation.
In a coarse locking operation of a DLL, if a coarse locking window is not adjusted to correspond to a frequency band, a failure of a coarse locking may occur in a frequency band of the DLL.
For these reasons, there is a need for an improved DLL circuit capable of preventing or minimizing a failure of a coarse locking during a locking operation of a DLL.